VgaSim

Open Source VGA simulator

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Welcome to the VgaSim Project Site

What is VgaSim?

VgaSim simulates a VGA screen connected to your VHDL design. Simulated signals from your desing will handle the virtual VGA screen such as it were real. The screen will loop the screens you simulate.

VgaSim works with VHDL abd VeriLog simulators such as ModelSim and GHDL porting the output simulation file as screens handled by a VGA Monitor. It use five signals to generate the images, this are Horizontal Sync, Vertical Sync, Red, Green and Blue.

The project is still under development, thats why several functions are not ready, you can find the feautures in the About VgaSim section.

You are welcome to contribute with the development of VgaSim and reporting bugs.

Why you should use VgaSim?

Simulating Vga is very difficult in the VHDL and VeriLog simulation softwares, because they show a stream of data in a graphic and we can only see 0's and 1's. They don't provided any tools to actually see the screens you are generating. If you don't have a prototyping board kit of FPGA or similar you could not check the proper working of your design.

Who should use VgaSim?

VgaSim is intendeed fot Ingeneer Student, or designers who are working with FPGA devices. You should know how to use ModelSim or GHDL to use VgaSim, we don't provide any support for these softwares.

Who Created VgaSim?

The first release of VgaSim 1.0.0a was writen by Fernando Caamaño, and is the current maintainer of the project. Other people who may want to participate are welcome.

Why VgaSim was created?

In order to test and debug several designs for the university. The FPGA development was introduced to me in the University of Buenos Aires (FIUBA) in the professorship "66.17 Sistemas Digitales". The site of this is http://cactus.fi.uba.ar and it has very useful information for FPGA development.

 

 

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